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XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FEBRUARY 2004 REV. 1.0.2
GENERAL DESCRIPTION
The XRT75L00 is a single-channel fully integrated Line Interface Unit (LIU) with Jitter Attenuator for E3/ DS3/STS-1 applications. It incorporates an independent Receiver, Transmitter and Jitter Attenuator in a single 52 pin TQFP package. The XRT75L00 can be configured to operate in either E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz) modes. The transmitter can be turned off (tristated) for redundancy support and for conserving power. The XRT75L00's differential receiver provides high noise interference margin and is able to receive the data over 1000 feet of cable or with up to 12 dB of cable attenuation. The XRT75L00 incorporates an advanced crystalless jitter attenuator that can be selected either in the transmit or receive path. The jitter attenuator performance meets the ETSI TBR-24 and Bellcore GR-499 specifications. The XRT75L00 provides both Serial Microprocessor Interface as well as Hardware mode for programming and control. The XRT75L00 supports local, remote and digital loop-backs. The XRT75L00 also contains an onboard Pseudo Random Binary Sequence (PRBS) generator and detector with the ability to insert and detect single bit error.
* On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
* Provides low jitter output clock.
TRANSMITTER:
* Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
* Tri-state Transmit output capability for redundancy
applications
* Transmitter can be turned on or off.
JITTER ATTENUATOR:
* On chip advanced crystal-less Jitter Attenuator. * Jitter Attenuator can be selected in Receive or
Transmit paths.
* 16 or 32 bits selectable FIFO size. * Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore GR-253 and GR-499 standards.
* Jitter Attenuator can be disabled.
CONTROL AND DIAGNOSTICS:
* 5 wire Serial Microprocessor Interface for control
and configuration.
* Supports
optional
internal
Transmit
Driver
FEATURES
RECEIVER:
Monitoring.
* On chip Clock and Data Recovery circuit for high
input jitter tolerance.
* Meets
E3/DS3/STS-1 Requirements.
Jitter
Tolerance
* Detects and Clears LOS as per G.775. * Meets Bellcore GR-499 CORE Jitter Transfer
Requirements.
* PRBS error counter register to accumulate errors. * Hardware Mode for control and configuration. * Supports Local, Remote and Digital Loop-backs. * Single 3.3 V 5% power supply. * 5 V Tolerant I/O. * Available in 52 pin TQFP. * -40C to 85C Industrial Temperature Range.
* Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
APPLICATIONS
* E3/DS3 Access Equipment. * DSLAMs. * Digital Cross Connect Systems. * CSU/DSU Equipment. * Routers. * Fiber Optic Terminals.
* Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995 standards.
* Meets ETSI TBR 24 Jitter Transfer Requirements. * On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L00
SDI SDO INT SClk CS RESET HOST/HW STS-1/DS3 E3 REQEN RTIP RRING SR/DR LLB
XRT75L03
Serial Processor Interface
CLK_OUT ExClk/12M RLOL RxON RxClkINV
Peak Detector Slicer Clock & Data Recovery LOS Detector
Clock Synthesizer Jitter Attenuator
Invert HDB3/ B3ZS Decoder
RxClk RPOS RNEG/ LCV
AGC/ Equalizer
MUX
Local LoopBack
Remote LoopBack
RLB RLOS JATx/Rx TPData TNData TxClk TAOS TxLEV TxON
TTIP TRING MTIP MRING DMO
Line Driver
Tx Pulse Shaping
Timing Control
Jitter Attenuator
MUX
HDB3/ B3ZS Encoder
Device Monitor
Tx Control
Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.
TRANSMIT INTERFACE CHARACTERISTICS
* Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line.
* Integrated Pulse Shaping Circuit. * Built-in B3ZS/HDB3 Encoder (which can be disabled). * Accepts Transmit Clock with duty cycle of 30%-70%. * Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications. * Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and
ANSI T1.102_1993.
* Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE. * Transmitter can be turned off in order to support redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
* Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery. * Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications. * Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications. * Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications. * Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms. * Built-in B3ZS/HDB3 Decoder (which can be disabled).
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REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
* Recovered Data can be muted while the LOS Condition is declared. * Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment.
JITTER ATTENUATORS
The XRT75L00 includes a Jitter Attenuator that meets the Jitter requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR-253 standards. In addition, the jitter attenuator also meets the Jitter and Wander specifications described in the ANSI T1.105.03b 1997, Bellcore GR-253 and GR-499 standards. FIGURE 2. PIN OUT OF THE XRT75L00
DMO MTIP MRING JaAGND ExClk/12M JaAVDD TxClk TPData TNData DGND TTIP TRING DVDD
39 38 37 36 35 34 33 32 31 30 29 28 27
CLK_OUT RPOS RNEG (LCV) RxClk GND RefAGND Rext RefAVDD VDD RLOS RLOL INT (LOSMUT) SDO (RxMON)
40 41 42 43 44 45 46 47 48 49 50 51 52
XRT75L00
(top view)
26 25 24 23 22 21 20 19 18 17 16 15 14
SCLK (TxClkINV) SDI (RxON) CS (RxClkINV) REQEN SR/DR HOST/HW E3 STS1/DS3 RLB LLB ICT TEST RESET
PART NUMBER XRT75L00IV
TxLEV TAOS TxAVDD TxON TxAGND JA0 JA1 JA Tx/Rx SFM_EN RxAVDD RRING RTIP RxAGND
1 2 3 4 5 6 7 8 9 10 11 12 13
ORDERING INFORMATION
PACKAGE 52 Pin TQFP OPERATING TEMPERATURE RANGE -40C to +85C
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
FEATURES ..................................................................................................................................................................... 1 APPLICATIONS ............................................................................................................................................................... 1 TRANSMIT INTERFACE CHARACTERISTICS ....................................................................................................................... 2 RECEIVE INTERFACE CHARACTERISTICS ......................................................................................................................... 2
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L00 ..................................................................................................................................... 2
JITTER ATTENUATORS.................................................................................................................................................... 3
FIGURE 2. PIN OUT OF THE XRT75L00 .................................................................................................................................................. 3
ORDERING INFORMATION.....................................................................................................................3
TABLE OF CONTENTS I
PIN DESCRIPTIONS (BY FUNCTION) .......................................................................................... 4
TRANSMIT INTERFACE .................................................................................................................................................... 4 RECEIVE INTERFACE ...................................................................................................................................................... 6 CLOCK INTERFACE......................................................................................................................................................... 8 OPERATING MODE SELECT............................................................................................................................................ 9 CONTROL AND ALARM INTERFACE .................................................................................................................................. 9 MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)......................................................................................... 11 ................................................................................................................................................................................... 13 JITTER ATTENUATOR INTERFACE .................................................................................................................................. 13 ANALOG POWER AND GROUND .................................................................................................................................... 14 DIGITAL POWER AND GROUND .................................................................................................................................... 14
1.0 ELECTRICAL CHARACTERISTICS ....................................................................................................15
TABLE 1: ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 15 TABLE 2: DC ELECTRICAL CHARACTERISTICS:....................................................................................................................................... 15
2.0 TIMING CHARACTERISTICS ..............................................................................................................16
FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75L00 (DUAL-RAIL DATA) ................................................. 16 TRANSMITTER TERMINAL INPUT TIMING................................................................................................................................. 16 RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING .......................................................................................................... 17 TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES ....................................................................... 17
3.0 LINE SIDE CHARACTERISTICS: ........................................................................................................18
3.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 18
FIGURE 7. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703 ............................................................................... 18 TABLE 3: E3 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD = 3.3 V 5%) .......................................... 18 FIGURE 8. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ................................... 19 TABLE 4: STS-1 PULSE MASK EQUATIONS ........................................................................................................................................... 19 TABLE 5: STS-1 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD =3.3V 5%)................................... 20 FIGURE 9. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ........................................................................... 20 TABLE 6: DS3 PULSE MASK EQUATIONS............................................................................................................................................... 21 TABLE 7: DS3 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD = 3.3V 5%) ...................................... 21 FIGURE 10. MICROPROCESSOR SERIAL INTERFACE STRUCTURE ............................................................................................................ 22 FIGURE 11. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ....................................................................................... 22 TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V 5% AND LOAD = 10PF) ........................................ 23
4.0
THE TRANSMITTER SECTION: .........................................................................................................24
4.1 TRANSMIT CLOCK: ....................................................................................................................................... 24 4.2 B3ZS/HDB3 ENCODER: ................................................................................................................................. 24
4.2.1 B3ZS ENCODING: ...................................................................................................................................................... 24 FIGURE 12. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED) .................................................................. 24 FIGURE 13. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED).................................................................................... 24 4.2.2 HDB3 ENCODING:...................................................................................................................................................... 25 FIGURE 14. B3ZS ENCODING FORMAT ................................................................................................................................................. 25 FIGURE 15. HDB3 ENCODING FORMAT ................................................................................................................................................. 25
4.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 26
4.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT: ................................................................................. 26 4.3.2 INTERFACING TO THE LINE: .................................................................................................................................... 26
4.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 26 4.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 27
FIGURE 16. TRANSMIT DRIVER MONITOR SET-UP................................................................................................................................... 27
5.0 THE RECEIVER SECTION ..................................................................................................................28
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
5.1 AGC/EQUALIZER ........................................................................................................................................... 28
5.1.1 INTERFERENCE TOLERANCE.................................................................................................................................. 28 FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1 ...................................................................................................... 29 FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3. ................................................................................................................... 29 TABLE 9: INTERFERENCE MARGIN TEST RESULTS ................................................................................................................................. 29
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 30 5.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 30 5.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 30
5.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 30
DISABLING ALOS/DLOS DETECTOR:........................................................................................................................... 30
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 30 TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS-1 APPLICATIONS).......................................................................................................................................................................... 30 FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775 ................................................................................................ 31 FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775................................................................................................. 31 5.4.2.1 MUTING THE RECOVERED DATA WITH LOS CONDITION: ......................................................................................... 32
6.0 JITTER: ................................................................................................................................................ 33
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 33
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 33 FIGURE 21. JITTER TOLERANCE MEASUREMENTS .................................................................................................................................. 33 6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 34 FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1 ...................................................................................................................... 34 FIGURE 23. INPUT JITTER TOLERANCE FOR E3 .................................................................................................................................... 34
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 35 6.3 JITTER GENERATION: .................................................................................................................................. 35 6.4 JITTER ATTENUATOR: ................................................................................................................................. 35
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ......................................................................... 35 TABLE 12: JITTER TRANSFER SPECIFICATIONS ...................................................................................................................................... 35 TABLE 13: JITTER TRANSFER PASS MASKS........................................................................................................................................... 36 FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE ...................................................................... 36
7.0 SERIAL HOST INTERFACE: ............................................................................................................... 37
TABLE 14: TABLE 15: TABLE 16: TABLE 17: FUNCTIONS OF SHARED PINS................................................................................................................................................ 37 REGISTER MAP AND BIT NAMES........................................................................................................................................... 37 REGISTER MAP DESCRIPTION .............................................................................................................................................. 39 REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................................................... 43
8.0 DIAGNOSTIC FEATURES: ................................................................................................................. 44
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 44 8.2 LOOPBACKS: ................................................................................................................................................ 44
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 44 FIGURE 25. PRBS MODE ................................................................................................................................................................... 44 8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 45 FIGURE 26. ANALOG LOOPBACK ........................................................................................................................................................... 45 FIGURE 27. DIGITAL LOOPBACK ............................................................................................................................................................ 45 8.2.3 REMOTE LOOPBACK:............................................................................................................................................... 46
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 46
FIGURE 28. REMOTE LOOPBACK........................................................................................................................................................... 46 FIGURE 29. TRANSMIT ALL ONES (TAOS) ............................................................................................................................................ 46
ORDERING INFORMATION ............................................................................................................................................. 47
PACKAGE DIMENSIONS ............................................................................................................. 47
REVISION HISTORY ...................................................................................................................................................... 48
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
PIN # 4 SIGNAL NAME TxON TYPE I DESCRIPTION
Transmitter ON Input
Setting this input pin "High" turns on the Transmitter.
NOTES: 1. Even when the XRT75L00 is configured in HOST mode, this pin still controls the TTIP and TRING outputs 2. When the Transmitter is turned off either in Host or Hardware mode,the TTIP and TRING outputs are Tri-stated. 3. This pin is internally pulled down
46 TxClk I
Transmit Clock Input for TPData and TNData
The frequency accuracy of this input clock must be of nominal bit rate 20 ppm. The duty cycle can be 30%-70%. The XRT75L00 samples the TPData and TNData pins on the falling or rising edge of TxClk signal based on the status of TxClkINV pin (in Hardware mode) or the status of the bit in the Channel Register (in HOST mode).
26
TxClkINV/ SClk
I
Transmit Clock Invert or Serial Clock Input: Function of this depends on whether the XRT75L00 is configured to operate in Hardware mode or Host mode. In Hardware mode, setting this input pin "High" configures the Transmitter to sample the TPData and TNData data on the rising edge of the TxClk.
NOTE: If the XRT75L00 is configured in HOST mode, this pin functions as SClk input pin (please refer to the pin description for Microprocessor interface).
48 TNData I
Transmit Negative Data Input
If the XRT75L00 is configured in Dual-rail mode, this pin is sampled on the falling or rising edge of TxClk based on the status of the TClkINV pin (in Hardware mode) or the status of the control bit in the Channel Register (in HOST mode). NOTES:
1. This input pin is ignored and should be tied to GND if the Transmitter Section is configured to accept Single-Rail data from the Terminal Equipment.
47 TPData I
Transmit Positive Data Input
The XRT75L00 samples this pin on the falling or rising edge of TxClk based on the status of the TClkINV pin (in Hardware mode) or the status of the control bit in the Channel Register (in HOST mode).
50
TTIP
O
Transmit TTIP Output
The XRT75L00 uses this pin along with TRING to transmit a bipolar signal to the line using a 1:1 transformer.
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TRANSMIT INTERFACE
PIN # 51 SIGNAL NAME TRING TYPE O DESCRIPTION
Transmit Ring Output
The XRT75L00 uses this pin along with TTIP to transmit a bipolar signal to the line using a 1:1 transformer.
1
TxLEV
I
Transmit Line Build-Out Enable/Disable Select This input pin is used to enable or disable the Transmit Line Build-Out circuit. Setting this pin to "High" disables the Line Build-Out circuit. In this mode, partially-shaped pulses are output onto the line via the TTIP and TRING output pins. Setting this pin to "Low" enables the Line Build-Out circuit. In this mode, shaped pulses are output onto the line via the TTIPand TRING output pins. To comply with the Isolated DSX-3/STSX-1 Pulse Template Requirements per Bellcore GR-499-CORE or Bellcore GR-253-CORE: 1. Set this pin to "1" if the cable length between the Cross-Connect and the transmit output is greater than 225 feet. 2. Set this pin to "0" if the cable length between the Cross-Connect and the transmit output is less than 225 feet. This pin is active only if the following two conditions are true: a. The XRT75L00 is configured to operate in either the DS3 or SONET STS-1 Modes. b. The XRT75L00 is configured to operate in the Hardware Mode.
NOTES: 1. 2. This pin is internally pulled down. If the XRT75L00 is configured in HOST mode, this pin may be tied to GND.
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
RECEIVE INTERFACE
PIN # 25 SIGNAL NAME RxON/ SDI TYPE I DESCRIPTION Receiver Turn ON Input or Serial Data Input: Function of this pin depends on whether the XRT75L00 is configured to operate in Hardware mode or Host mode. In Hardware mode, setting this input pin "High" turns on and enables the Receiver..
NOTES: 1. If the XRT75L00 is configured in HOST mode, this pin functions as SDI input pin (please refer to the pin description for Microprocessor Interface) This pin is internally pulled down.
2.
23 REQEN I
Receive Equalization Enable Input Setting this input pin "High" enables the Internal Receive Equalizer. Setting this pin "Low" disables the Internal Receive Equalizer.
NOTES: 1. This input pin is ignored and may be connected to GND if the XRT75L00 is operating in the HOST Mode 2. This pin is internally pulled down.
36 RxClk O Receive Clock Output The Recovered Clock signal from the incoming line signal is output through this pin.By default, the Receiver Section outputs data via RPOS and RNEG pins on the rising edge of this clock signal. Configure the Receiver Section to update data on the RPOS and RNEG pins on the falling edge of RxClk by doing the following: a) Operating in Hardware mode, pull the RxClkINV pin to "High". b) Operating in Host mode, write a "1" to RxClkINV bit field within the Receive Control Register. RxClk INVERT or Chip Select: Function of this pin depends on whether the XRT75L00 is configured to operate in Hardware mode or Host mode. In Hardware mode, setting this input pin "High" configures the Receiver Section to invert the RxClk output signals and outputs the recovered data via RPOS and RNEG on the falling edge of RxClk.
24
RxClkINV/ CS
I
NOTE: If the XRT75L00 is configured in HOST mode, this pin functions as CS input pin (please refer to the pin description for Microprocessor Interface).
38 RPOS O
Receive Positive Data Output
This output pin pulses "High" whenever the XRT75L00 has received a Positive Polarity pulse in the incoming line signal at the RTIP/RRing inputs.
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
RECEIVE INTERFACE
PIN # 37 SIGNAL NAME RNEG/LCV TYPE O DESCRIPTION
Receive Negative Data Output/Line Code Violation Indicator
Function of these pins depends on whether the XRT75L00 is configured in Single Rail or Dual Rail mode. If the XRT75L00 is configured in Dual Rail mode, a negative pulse is output through RNEG. In Hardware mode: Tie the pin SR/DR (pin 22) "High" to configure the XRT75L00 in Single Rail mode and tie "Low" to configure in Dual Rail mode. In HOST mode: XRT75L00 can be configured in Single Rail or Dual Rail by setting or clearing the bit in the block control register.
Line Code Violation Indicator
If the XRT75L00 is configured in Single Rail mode then: Whenever the Receiver Section detects a Line Code violation, it pulses this output pin "High". This output pin remains "Low" at all other times. It is advisable to sample this output pin using the RxClk output signal. 11 RRING I
Receive Ring Input
This input pin along with RTIP is used to receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal.
12
RTIP
I
Receive TIP Input
This input pin along with RRNG is used to receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal.
27
RxMON/ SDO
I
Receive Monitoring Mode or Serial Data Output: In Hardware mode, when this pin is tied "High" XRT75L00 configures into monitoring channel. In the monitoring mode, the Receiver is capable of monitoring the signals with 20 dB flat loss plus 6 dB cable attenuation. This allows to monitor very weak signal before declaring LOS. In HOST Mode, XRT75L00 can be configured to be a monitoring channel by setting the bits in the receive control register.
NOTE: If the XRT75L00 is configured in HOST mode, this pin functions as SDO pin (please refer to the pin description for the Microprocessor Interface).
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
CLOCK INTERFACE
PIN # 44 SIGNAL NAME ExClk/12M TYPE I DESCRIPTION Clock Input (34.368 MHz or 44.736 MHz or 51.84 MHz 20 ppm): Based on the mode selected, provide the appropriate reference clock signal. If the XRT75L00 is configured for Single Frequency Mode with the SFM_EN tied "High", then provide a 12.288 MHz 20 ppm clock and depending on the mode, the correct frequency is generated internally by the clock synthesizer.. 9 SFM_EN I Single Frequency Enable: Tie this pin "High" to select the single frequency mode. When enabled, a single frequency clock, 12.288 MHz is input through the ExClk input pin and the internal clock synthesizer generates the appropriate clock frequency.
NOTE: This pin is internally pulled down.
39 CLK_OUT O Clock out put: When the Single Frequency Mode is selected, a low jitter clock will be out put. The frequency of this clock depends on whether the XRT75L00 is configured in E3 or DS3 or STS-1 mode.
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OPERATING MODE SELECT
PIN # 21 SIGNAL NAME HOST/(HW) TYPE I DESCRIPTION HOST/Hardware Mode Select: Tie this pin "High" to configure the XRT75L00 in HOST mode. Tie this "Low" to configure in Hardware mode. When the XRT75L00 is configured in HOST mode, the states of many discrete input pins are ignored.
NOTE: This pin is internally pulled up.
20 E3 I E3 Mode Select Input A "High" on this pin configures to operate in the E3 mode. A "Low" on this pin configures to operate in either STS-1 or DS3 mode depending on the setting on pin 19.
NOTES: 1. This pin is internally pulled down 2. This pin is ignored and may be tied to GND if the XRT75L00 is configured to operate in HOST mode.
19 STS-1/DS3 I STS-1/DS3 Select Input A "High" on this pin configures to operate in STS-1 mode. A "Low" on this pin configures to operate in DS3 mode. This pin is ignored if the E3 pin is set to "High".
NOTES: 1. This pin is internally pulled down 2. This pin is ignored and may be tied to GND if the XRT75L00 is configured to operate in HOST mode.
22 SR/DR I Single-Rail/Dual-Rail Select: Setting this "High" configures both the Transmitter and Receiver to operate in Single-rail mode and also enables the B3ZS/HDB3 Encoder and Decoder. In Single-rail mode, Transmit input at TNData should be grounded. Setting this "Low" configures both the Transmitter and Receiver to operate in Dual-rail mode and disables the B3ZS/HDB3 Encoder and Decoder.
NOTE: This pin is internally pulled down.
CONTROL AND ALARM INTERFACE
42 MRING I
Monitor Ring Input
The bipolar line output signal from TRING is connected to this pin via a 270 resistor to check for line driver failure.
NOTE: This pin is internally pulled down.
41 MTIP I
Monitor Tip Input
The bipolar line output signal from TTIP is connected to this pin via a 270-ohm resistor to check for line driver failure.
NOTE: This pin is internally pulled down.
40 DMO O
Drive Monitor Output
If MTIP and MRING has no transition pulse for 128 32 TxClk cycles, DMO goes "High" to indictae the driver failure. DMO output stays "High" until the next AMI signal is detected.
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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CONTROL AND ALARM INTERFACE
30 RLOS O
Receive Loss of Signal Output Indicator
This output pin toggles "High" if Receiver has detected a Loss of Signal Condition in the incoming line signal. The criteria for declaring/clearing an LOS Condition depends upon whether it is operating in the E3 or STS-1/DS3 Mode and is described in Section 2.04.
29
RLOL
O
Receive Loss of Lock Output Indicator:
This output pin toggles "High" if the XRT75L00 has detected a Loss of Lock Condition. LOL (Loss of Lock) condition is declared if the recovered clock frequency deviates from the Reference Clock frequency (available at ExClk input pin) by more than 0.5%.
33
Rext
****
External Bias control Resistor of 3.3 K 1%. Should be connected to RefAGND via 3.3 K resistor. Test Mode: Connect this pin "High" to configure the XRT75L00 in test mode.
15
TEST
I
NOTE: This pin is internally pulled Down.
16 ICT I
In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a highimpedance state to allow for in-circuit testing. For normal operation, set this pin "High".
NOTE: This pin is internally pulled "High".
2 TAOS I
Transmit All Ones Select
A "High" on this pin causes the Transmitter Section to generate and transmit a continuous AMI all "1's" pattern onto the line. The frequency of this "1's" pattern is determined by TxClk. NOTES:
1. This input pin is ignored if the XRT75L00 is operating in the HOST Mode and should be tied to GND. 2. Analog Loopback and Remote Loopback have priority over request. 3. This pin is internally pulled down.
28 LOSMUT/ INT I/O MUTE-upon-LOS Enable Input or Interrupt Ouput: In Hardware Mode, setting this pin "High" configures the XRT75L00 to Mute the recovered data on the RPOS and RNEG whenever an LOS condition is declared. RPOS and RNEG outputs are pulled "Low".
NOTE:
If the XRT75L00 is configured in HOST mode, this pin functions as INT pin (please refer to the pin description for the Microprocessor Interface).
10
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
CONTROL AND ALARM INTERFACE
17 LLB I
Local Loop-back
This input pin along with RLB configures different Loop-Back modes.
RLB 0 0 1 1
LLB 0 1 0 1
Loopback Mode Normal Operation Analog Local Remote Digital
NOTE: This input pin is ignored and may be connected to GND if the XRT75L00 is operating in the HOST Mode.
18 RLB I
Remote Loop-back
This input pin along with LLB configures different Loop-Back modes.
NOTE:
This input pin is ignored and should be connected to GND if the XRT75L00 is operating in the HOST Mode.
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)
PIN # 24 SIGNAL NAME CS/RxClkINV TYPE I DESCRIPTION Microprocessor Serial Interface - Chip Select Tie this "Low" to enable the communication with Serial Microprocessor Interface.
NOTE: If the XRT75L00 is configured in Hardware Mode,this pin functions as RxClkINV.
26 SCLK/TxClkINV I Serial Interface Clock Input The data on the SDI pin is sampled on the rising edge of this signal. Additionally, during Read operations the Microprocessor Serial Interface updates the SDO output on the falling edge of this signal.
NOTE: If the XRT75L00 is configured in Hardware Mode, this pin functions as TxClkINV.
25 SDI/RxON I Serial Data Input: Data is serially input through this pin. The input data is sampled on the rising edge of the SCLK pin (pin 26).
NOTES: 1. This pin is internally pulled down 2. If the XRT75L00 is configured in Hardware Mode, this pin functions as RxON.
27 SDO/RxMON O Serial Data Output: This pin serially outputs the contents of the specified Command Register during Read Operations. The data is updated on the falling edge of the SCLK and this pin is tri-stated upon completion of data transfer.
NOTE: If the XRT75L00 is configured in Hardware Mode, this pin functions as RxMON.
11
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)
PIN # 14 SIGNAL NAME RESET TYPE I DESCRIPTION
Register Reset:
Setting this input pin "Low" causes the XRT75L00 to reset the contents of the Command Registers to their default settings and default operating configuration
NOTE: This pin is internally pulled up.
28 INT/LOSMUT I/O INTERRUPT Output: This pin functions as Interrupt Output for Serial Interface. A transition to "Low" indicates that an interrupt has been generated by the Serial Interface. The interrupt function can be disabled by setting the interrupt enable bit to "0" in the Channel Control Register.
NOTE: If the XRT75L00 is in Hardware mode, this pin functions as LOSMUT.
12
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
JITTER ATTENUATOR INTERFACE
PIN # 6 SIGNAL NAME JA0 TYPE I DESCRIPTION Disable Jitter Attenuator/FIFO Size Select:: In Hardware Mode, this pin along with JA1 pin provides the following functions in the table below.
JA0 0 0 1 1
JA1 0 1 0 1
Operation 16 bit FIFO 32 bit FIFO Disable Jitter Attenuator Disable Jitter Attenuator
NOTE: This pin is internally pulled down.
7 JA1 I Disable Jitter Attenuator/FIFO Size Select: In Hardware Mode, this pin along with JA0 pin provides the functions in the table above.
NOTE: This pin is internally pulled down.
8 JA Tx/Rx I Jitter Attenuator Select: In Hardware Mode setting this pin "High" selects the Jitter Attenuator in the Transmit path and setting "Low" selects in Receive path.
NOTE: This pin is internally pulled down.
13
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
ANALOG POWER AND GROUND
PIN # 3 10 32 5 13 34 45 43 SIGNAL NAME TxAVDD RxAVDD RefAVDD TxAGND RxAGND RefAGND JaAVDD JaAGND TYPE **** **** **** **** **** **** **** **** DESCRIPTION
Transmitter Analog VDD 3.3 V 5% Receiver Analog VDD 3.3 V 5% Reference Analog VDD 3.3 V 5% Transmitter Analog GND Receiver Analog GND Reference Analog GND Jitter Attenuator Analog VDD 3.3 V 5% Jitter Attenuator Analog GND
DIGITAL POWER AND GROUND
PIN # 31 35 52 49 SIGNAL NAME DVDD DGND DVDD DGND TYPE **** **** **** **** DESCRIPTION
VDD 3.3 V 5% Receiver Digital GND VDD 3.3 V 5% Transmitter Digital GND
14
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
1.0 ELECTRICAL CHARACTERISTICS TABLE 1: ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER Supply Voltage Input Voltage at any Pin Input current at any pin Storage Temperature Ambient Operating Temperature Thermal Resistance
MIN
MAX
UNITS
COMMENTS
VDD VIN IIN STEMP ATEMP ThetaJA ThetaJC MLEVL ESD
-0.5 -0.5
6.0 5+0.5 100
V V mA
0 0
Note 1 Note 1 Note 1 Note 1 linear airflow 0 ft./min linear air flow 0ft/min
-65 -40
150 85 20 6
C C
0C/W 0
C/W EIA/JEDEC JESD22-A112-A Note 2
Exposure to Moisture ESD Rating
5 2000
level V
NOTES: 1. Exposure to or operating near the Min or Max values for extended period may cause permanent failure and impair reliability of the device. 2. ESD testing method is per MIL-STD-883D,M-3015.7
TABLE 2: DC ELECTRICAL CHARACTERISTICS:
SYMBOL
PARAMETER Digital Supply Voltage Analog Supply Voltage Supply current (Measured while transmitting and receiving all 1's) Power Dissipation Input Low Voltage Input High Voltage Output Low Voltage, IOUT = - 4mA Output High Voltage, IOUT = 4 mA Input Leakage Current1
MIN.
TYP.
MAX.
UNITS
DVDD AVDD ICC PDD VIL VIH VOL VOH IL CI CL
3.135 3.135 75 235
3.3 3.3 150 495
3.465 3.465 225 780 0.8
V V mA mW V V V V A pF pF
2.0
5.0 0.4
2.4 10 10 10
Input Capacitance Load Capacitance
NOTES: 1. Not applicable for pins with pull-up or pull-down resistors. 2. The Digital inputs and outputs are TTL 5V compliant.
15
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 2.0 TIMING CHARACTERISTICS
REV. 1.0.2
FIGURE 3. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75L00 (DUAL-RAIL DATA)
TxPOS Terminal Equipment (E3/DS3 or STS-1 Framer) TxNEG TxLineClk
TPData TNData TxClk
Transmit Logic Block
Exar E3/DS3/STS-1 LIU
FIGURE 4. TRANSMITTER TERMINAL INPUT TIMING
t RTX TxClk t TSU TPData or TNData TTIP or TRing t TDY t THO t FTX
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TxClk
Duty Cycle E3 DS3 STS-1 TxClk Rise Time (10% to 90%) TxClk Fall Time (10% to 90%) TPData/TNData to TxClk falling set up time TPData/TNData to TxClk falling hold time TTIP/TRing to TxClk rising propagation delay time
30
50 34.368 44.736 51.84
70
% MHz MHz MHz ns ns ns ns
tRTX tFTX tTSU tTHO tTDY
4 4 3 3 8
ns
16
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FIGURE 5. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING
tRRX RClk tLCVO LCV tCO RPOS or RNEG
tFRX
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
RxClk
Duty Cycle E3 DS3 STS-1 RxClk rise time (10% o 90%) RxClk falling time (10% to 90%) RxClk to RPOS/RNEG delay time RxClk to rising edge of LCV output delay
45
50 34.368 44.736 51.84 2 2
55
% MHz MHz MHz ns ns ns ns
tRRX tFRX tCO tLCVO
4 4 4
2.5
FIGURE 6. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES
TTIP
37.4 +1%
37.4 + 1%
TxPOS TxNEG TxLineClk
3.3k + 1%
R2
TPData TNData TxClk
Rext RefAGND
R1
R3 75 1:1
TRing
17
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 3.0 LINE SIDE CHARACTERISTICS: 3.1 E3 line side parameters:
REV. 1.0.2
The XRT75L00 meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation at the secondary of the transformer. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure 7. FIGURE 7. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703
17 ns (14.55 + 2.45)
V = 100%
8.65 ns
Nominal Pulse
50%
14.55ns 12.1ns (14.55 - 2.45) 10% 20%
10% 0%
TABLE 3: E3 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD = 3.3 V 5%)
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude (Measured at secondary of the transformer) Transmit Output Pulse Amplitude Ratio Transmit Output Pulse Width Intrinsic Jitter 0.90 0.95 12.5 1.00 1.00 14.55 0.02 1.10 1.05 16.5 0.05 ns UIPP feet dB UIPP -35 -15 10 10 255 255 dB dB UI UI Vpk
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable) Interference Margin Jitter Tolerance @ Jitter Frequency 800KHz Signal level to Declare Loss of Signal Signal Level to Clear Loss of Signal Occurence of LOS to LOS Declaration Time Termination of LOS to LOS Clearance Time -20 0.15 1200 -15 0.28
18
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FIGURE 8. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
ST S-1 Pulse T emplate
1.2
1
0.8 Norm a liz e d Am plitude
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
0
-1
1
2
3
4
5
6
7
8
9
1
1
2
3 1.
9
8
7
6
5
4
3
2
1
0.
0.
0.
0.
0.
0.
0.
0.
0.
1.
1.
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
Time, in UI
TABLE 4: STS-1 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS LOWER CURVE -0.85 < T < -0.38 -0.38 - 0.03 NORMALIZED AMPLITUDE
< T < 0.36
T 0.5 1 + sin -- 1 + --------- - 0.03 2 0.18
- 0.03 UPPER CURVE
0.36 < T < 1.4 -0.85 < T < -0.68 -0.68 < T < 0.26
0.03
T 0.5 1 + sin -- 1 + --------- + 0.03 2 0.34
0.1 + 0.61 x e-2.4[T-0.26]
0.26 < T < 1.4
19
1.
4
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
TABLE 5: STS-1 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD =3.3V 5%)
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Intrinsic Jitter 0.65 0.90 8.6 0.90 0.75 1.00 9.65 1.00 0.02 0.90 1.10 10.6 1.10 0.05 UIpp feet UIpp Vpk Vpk ns
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable) Jitter Tolerance @ Jitter Frequency 400 KHz Signal Level to Declare Loss of Signal Signal Level to Clear Loss of Signal 900 0.15 1100 0.60 Refer to Table 10 Refer to Table 10
FIGURE 9. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499
DS3 Pulse T emplate
1.2
1
0.8 Norm a lize d Am plitude
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
-1
0
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
1
1
2
3 1.
0.
0.
0.
0.
0.
0.
0.
0.
0.
1.
1.
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
-0 .
Tim e , in UI
20
1.
4
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 6: DS3 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS LOWER CURVE -0.85 < T < -0.36 -0.36 - 0.03 NORMALIZED AMPLITUDE
< T < 0.36
T 0.5 1 + sin -- 1 + --------- - 0.03 2 0.18
- 0.03 UPPER CURVE
0.36 < T < 1.4 -0.85 < T < -0.68 -0.68 < T < 0.36
0.03
T 0.5 1 + sin -- 1 + --------- + 0.03 2 0.34
0.08 + 0.407 x e-1.84[T-0.36]
0.36 < T < 1.4
TABLE 7: DS3 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD = 3.3V 5%)
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Intrinsic Jitter 0.65 0.90 10.10 0.90 0.75 1.00 11.18 1.00 0.02 0.85 1.10 12.28 1.10 0.05 UIpp Vpk Vpk ns
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable) Jitter Tolerance @ 400 KHz (Cat II) Signal Level to Declare Loss of Signal Signal Level to Clear Loss of Signal 900 0.15 1100 0.60 Refer to Table 10 Refer to Table 10 feet UIpp
21
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
FIGURE 10. MICROPROCESSOR SERIAL INTERFACE STRUCTURE
CS
SClk
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
R/W
A0
A1
A2
A3
A4
A5
0
D0
D1
D2
D3
D4
D5
D6
D7
High Z SDO
D0 D1 D2 D3 D4 D5 D6 D7
High Z
FIGURE 11. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t28 CS t21 t26 SCLK t 22 SDI t 23 R/W A0 A1 t 24 t 25 t27
CS
SCLK t29 SDO Hi-Z D0 t30 D1 Hi-Z t 32 D2 D7 t 31
SDI
22
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V 5% AND LOAD = 10PF)
SYMBOL t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 PARAMETER CS Low to Rising Edge of SClk SDI to Rising Edge of SClk SDI to Rising Edge of SClk Hold Time SClk "Low" Time SClk "High" Time SClk Period Falling Edge of SClk to rising edge of CS CS "Inactive" Time Falling Edge of SClk to SDO Valid Time Falling Edge of SClk to SDO Invalid Time Rising edge of CS to High Z Rise/Fall time of SDO Output 10 5 0 50 20 10 MIN. 5 5 5 25 25 50 TYP. MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
23
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 4.0 THE TRANSMITTER SECTION:
REV. 1.0.2
The Transmitter Section accepts TTL/CMOS level signals from the Terminal Equipment in the selectable data formats.
* In Single-Rail or un-encoded Non-Return-to-Zero (NRZ) input data via TPData pin while the TNData pin
must be grounded. The NRZ or Single-Rail mode is selected when the SR/DR input pin is "High" (in Hardware Mode) or bit 0 of the control register is "1" (in Host Mode). Figure 12 illustrates the Single-Rail or NRZ format. FIGURE 12. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)
Data
1
1
0
TPData TxClk
* In Dual-Rail mode, data is input via TPData and TNData pins. TPData contains positive data and TNData
contains negative data. The SR/DR input pin = "Low" (in Hardware Mode) or bit 0 of the control register = "0" (in Host Mode) enables the Dual-Rail mode. Figure 13 illustrates the Dual-Rail data format. FIGURE 13. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED)
Data
1
1
0
TPData TNData TxClk
* Convert the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the
various industry standard pulse template requirements. Figure 7, Figure 8 and Figure 9 illustrate the pulse template requirements.
* Encode the un-encoded NRZ data into either B3ZS format (for DS3 or STS-1) or HDB3 format (for E3) and
convert to pulses with shapes and width that are compliant with industry standard pulse template requirements. Figure 7,Figure 8 and Figure 9 illustrate the pulse template requirements. 4.1 TRANSMIT CLOCK: The Transmit Clock applied via TxClk pin, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736 MHz or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle clock to the pulse shaping circuit. This allows a 30% to 70% duty cycle Transmit Clock be supplied and thus eliminates the need to use an expensive oscillator. 4.2 B3ZS/HDB3 ENCODER: When the Single-Rail (NRZ) data format is selected, the Encoder Block encodes the data into either B3ZS format (for either DS3 or STS-1) or HDB3 format (for E3). 4.2.1 B3ZS Encoding:
24
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
An example of B3ZS encoding is shown in Figure 14. If the encoder detects an occurrence of three consecutive zeros in the data stream, it is replaced with either B0V or 00V, where `B' refers to Bipolar pulse that is compliant with the Alternating polarity requirement of the AMI (Alternate Mark Inversion) line code and `V' refers to a Bipolar Violation (e.g., a bipolar pulse that violates the AMI line code). The substitution of B0V or 00V is made so that an odd number of bipolar pulses exist between any two consecutive violation (V) pulses. This avoids the introduction of DC component into the line signal. FIGURE 14. B3ZS ENCODING FORMAT
TClk TPDATA Line Signal
1 1 0 0 1 1 1 1 0 0 1 0 0 V 0 0 B 0 0 0 V B V 0 0 0
0 0
0 0
0 V
0 0
1
4.2.2
HDB3 Encoding:
An example of the HDB3 encoding is shown in Figure 15.If the HDB3 encoder detects an occurrence of four consecutive zeros in the data stream, then the four zeros are substituted with either 000V or B00V pattern. The substitution code is made in such a way that an odd number of bipolar (B) pulses exist between any consecutive V pulses. This avoids the introduction of DC component into the analog signal. FIGURE 15. HDB3 ENCODING FORMAT
TClk TPDATA Line Signal
1 1 0 0 1 11 1 0 0 0 0 0 0 0 V 1 1 0 0 0 0 0 0 V 0 0 B 0 0 0 0 0 V 0 0
NOTES: 1. When Dual-Rail data format is selected, the B3ZS/HDB3 Encoder is automatically disabled. 2. In Dual-Rail format, the Bipolar Violations in the incoming data stream is converted to valid data pulses. 3. Encoder and Decoder is enabled only in Single-Rail mode.
25
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 4.3 TRANSMIT PULSE SHAPER:
REV. 1.0.2
The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark Inversion (AMI) pulse that meet the industry standard mask template requirements for STS-1 and DS3. See Figure 8 and Figure 9. For E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped pulse with very little slope. This is illustrated in Figure 7. The Pulse Shaper Block also consists of a Transmit Build Out Circuit, which can either be disabled or enabled by setting the TxLEV input pin "High" or "Low" (in Hardware Mode) or setting the TxLEV bit to "1" or "0" in the control register (in Host Mode). For DS3/STS-1 rates, the Transmit Build Out Circuit is used to shape the transmit waveform that ensures that transmit pulse template requirements are met at the Cross-Connect system. The distance between the transmitter output and the Cross-Connect system can be between 0 to 450 feet. For E3 rate, since the output pulse template is measured at the secondary of the transformer and since there is no Cross-Connect system pulse template requirements, the Transmit Build Out Circuit is always disabled. 4.3.1 Guidelines for using Transmit Build Out Circuit: If the distance between the transmitter and the DSX3 or STSX-1, Cross-Connect system, is less than 225 feet, enable the Transmit Build Out Circuit by setting the TxLEV input pin "Low" (in Hardware Mode) or setting the TxLEV control bit to "0" (in Host Mode). If the distance between the transmitter and the DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit. 4.3.2 Interfacing to the line: The differential line driver increases the transmit waveform to appropriate level and drives into the 75 load as shown in Figure 6. 4.4 Transmit Drive Monitor: This feature is used for monitoring the transmit line for occurrence of fault conditions such as short circuit on the line or defective line driver.The device can also be configured for internal tranmit driver monitoring. To monitor the transmitter output of another chip, connect MTIP pin to the TTIP line via a 270 resistor and MRing pins to TRing line via 270 resistor as shown in Figure 16
26
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
In order to configure the device for internal transmit driver monitoring, set the TxMON bit to "1" in the transmit control register. FIGURE 16. TRANSMIT DRIVER MONITOR SET-UP.
T T IP
R1
3 7 .4 + 1 %
T xP O S T xN E G T x L in e C lk
3.3k + 1%
T P D a ta T N D a ta T x C lk
R e xt R e fA G N D
R2
3 7 .4 + 1 %
R3 75
1 :1 T R in g M T IP M R in g
XRT75L00
T xP O S T xN E G T x L in e C lk
T P D a ta T N D a ta T x C lk
M T IP M R in g T T IP
R1
R 4 270 R 5 270
3 7 .4 + 1 %
1 :1
3.3k + 1% R2
3 7 .4 + 1 %
R ext R e fA G N D
R3 75
T R in g
When the MTIP and MRing are connected to the TTIP and TRing lines, the drive monitor circuit monitors the line for transitions. The DMO (Drive Monitor Output) will be asserted "Low" as long as the transitions on the line are detected via MTIP and MRing. If no transitions on the line are detected for 128 32 TxClk periods, the DMO output toggles "High" and when the transitions are detected again, DMO toggles "Low".
NOTE: The Drive Monitor Circuit is only for diagnostic purposes and does not have to be used to operate the transmitter.
4.5
Transmitter Section On/Off:
The transmitter section can be turned on or off. To turn on the transmitter in the Hardware mode, pull TxON pin "High". In the Host mode, write a "1" to the TxON control bit AND pull the TxON pin "High" to turn on the transmitter. When the transmitter is turned off, the TTIP and TRing are tri-stated.
NOTES: 1. 2. This feature provides support for Redundancy. If the XRT75L00 is configured in Host mode, to permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a "1" to the TxON control bit transfers the control to TxON pin.
27
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 5.0 THE RECEIVER SECTION
REV. 1.0.2
This section describes the detailed operation of the various blocks in the receiver. The receiver recovers the TTL/CMOS level data from the incoming bipolar B3ZS or HDB3 encoded input pulses. 5.1 AGC/Equalizer The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the signal to reduce the Inter-Symbol Interference (ISI) so that, the slicer slices the signal at 50% of peak voltage to generate Positive and Negative data. The Equalizer can either be "IN" or "OUT" by setting the REQEN pin "High" or "Low" (in Hardware Mode) or setting the REQEN control bit to "1" or "0" (in Host Mode). RECOMMENDATIONS FOR EQUALIZER SETTINGS The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/ STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable, the Equalizer can be left "IN" by setting the REQEN pin to "High" (in Hardware Mode) or setting the REQEN control bit to "1" (in Host Mode). However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses (that does not meet the pulse template requirements), it is recommended that the Equalizer be left "OUT" for cable length less than 300 feet by setting the REQEN pin "Low" (in Hardware Mode) or by setting the REQEN control bit to "0" (in Host Mode).This would help to prevent over-equalization of the signal and thus optimize the performance in terms of better jitter transfer characteristics.
NOTE: The results of extensive testing indicates that even when the Equalizer was left "IN" (REQEN = "HIGH"), regardless of the cable length, the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at Industrial Temperature.
The Equalizer also contain an additional 20 dB gain stage to provide the line monitoring capability of the resistively attenuated signals which may have 20dB flat loss. This capability can be turned on by writing a "1" to the RxMON bits in the control register or by setting the RxMON pin (pin 27) "High". 5.1.1 Interference Tolerance For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error-free clock and data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same recommendation is being used. Figure 17 shows the configuration to test the interference margin for DS3/ STS1. Figure 18 shows the set up for E3.
28
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
ATTENUATOR SINE WAVE GENERATOR N
DS3 = 22.368 MHz STS-1 = 25.92 MHz
Cable Simulator
DUT XRT75L00 Test Equipment
PATTERN GENERATOR 223 - 1 PRBS
S
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3.
ATTENUATOR 1 ATTENUATOR 2
NOISE GENERATOR
N
Cable Simulator
DUT XRT75L00 Test Equipment
Pattern Generator
S
TABLE 9: INTERFERENCE MARGIN TEST RESULTS
MODE CABLE LENGTH (ATTENUATION) 0 dB E3 12 dB 0 feet DS3 225 feet 450 feet 0 feet STS-1 225 feet 450 feet INTERFERENCE TOLERANCE -14 dB -18 dB -17 dB -16 dB -16 dB -16 dB -15 dB -15 dB
29
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 5.2 Clock and Data Recovery:
REV. 1.0.2
The Clock and Data Recovery Circuit extracts the embedded clock, from the sliced digital data stream and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the following two modes: TRAINING MODE: In the absence of input signals at RTIP and RRing pins, or when the frequency difference between the recovered line clock signal and the reference clock applied on the ExClk input pin exceed 0.5%, the clock recovery unit enters into Training Mode and a Loss of Lock condition is declared by toggling RLOL output pin "High" (in Hardware Mode) or setting the RLOL bit to "1" in the control registers (in Host Mode). Also, the clock output on the RxClk pin is the same as the reference clock applied on ExClk pin. DATA/CLOCK RECOVERY MODE: In the presence of input line signals on the RTIP and RRing input pins and when the frequency difference between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on the RxClk out pin is the Recovered Clock signal. 5.3 B3ZS/HDB3 Decoder: The decoder block takes the output from clock and data recovery block and decodes the B3ZS (for DS3 or STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data stream. Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active "High" pulse is generated on the RLCV output pins to indicate line code violation.
NOTE: In Single- Rail (NRZ) mode, the decoder is bypassed.
5.4 5.4.1
LOS (Loss of Signal) Detector: DS3/STS-1 LOS Condition:
A Digital Loss of Signal (DLOS) condition occurs when a string of 175 75 consecutive zeros occur on the line. When the DLOS condition occurs, the DLOS bit is set to "1" in the status control register. DLOS condition is cleared when the detected average pulse density is greater than 33% for 175 75 pulses. Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the threshold as shown in the Table 10.The status of the ALOS condition is reflected in the ALOS status control register. RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS output pin is toggled "High" and the RLOS bit is set to "1" in the status control register. TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION DS3 STS-1 REQEN SETTING 1 1 SIGNAL LEVEL TO DECLARE ALOS <20mV <25mV SIGNAL LEVEL TO CLEAR ALOS >90mV >115mV
DISABLING ALOS/DLOS DETECTOR:
For debugging purposes it is useful to disable the ALOS/DLOS detector. Writing a "1" to the ALOS and DLOS bits disables the LOS detector on a per channel basis. 5.4.2 E3 LOS Condition: If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the LOS condition is detected. Loss of signal level is defined to be between 15 and 35 dB below the normal level. If
30
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
the signal drops below 35 dB for 175 75 consecutive pulse periods, LOS condition is declared. This is illustrated in Figure 19. FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB -15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
As defined in ITU-T G.775, an LOS condition is also declared between 10 and 255 UI (or E3 bit periods) after the actual time the LOS condition has occurred. The LOS condition is cleared within 10 to 255 UI after restoration of the incoming line signal. Figure 20 shows the LOS declaration and clearance conditions.
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.
Actual Occurrence of LOS Condition RTIP/ RRing Line Signal is Restored
10 UI
255 UI
Time Range for LOS Declaration
10 UI
255 UI
RLOS Output Pin 0 UI G.775 Compliance 0 UI Time Range for LOS Clearance G.775 Compliance
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 5.4.2.1 Muting the Recovered Data with LOS condition:
REV. 1.0.2
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the ExClk pin and output this clock on the RxClk output. The data on the RPOS and RNEG pins can be forced to zero by pulling the LOSMUT pin "High" (in Hardware Mode) or by setting the LOSMUT bits in the individual channel control register to "1" (in Host Mode).
NOTE: When the LOS condition is cleared, the recovered data is output on RPOS and RNEG pins.
32
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
6.0 JITTER: There are three fundamental parameters that describe circuit performance relative to jitter:
* Jitter Tolerance (Receiver) * Jitter Transfer (Receiver/Transmitter) * Jitter Generation
6.1 JITTER TOLERANCE - RECEIVER: Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error rate (BER). To measure the jitter tolerance as shown in Figure 21, jitter is introduced by the sinusoidal modulation of the serial data bit sequence. FIGURE 21. JITTER TOLERANCE MEASUREMENTS
Pattern Pattern Generator Generator
Data
DUT DUT XRT75L00 XRT75L00
Error Error Detector Detector
Clock Modulation Freq.
FREQ FREQ Synthesizer Synthesizer
Input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as a combination of points.Each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter frequency. 6.1.1 DS3/STS-1 Jitter Tolerance Requirements: Bellcore GR-499 CORE, Issue 1, December 1995 specifies the minimum requirement of jitter tolerance for Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 22 shows the jitter tolerance curve as per GR-499 specification along with the measured performance for the device.
33
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1
64 41 15 JITTER AMPLITUDE (UIpp) 10 5 1.5 0.3 0.15 0.1
GR-253 STS-1 GR-499 Cat II GR-499 Cat I XRT75L00
0.01
0.03
0.3
2
20
100
JITTER FREQUENCY (kHz)
6.1.2
E3 Jitter Tolerance Requirements:
ITU-T G.823 standard specifies that the clock and data recovery unit must be able to accommodate and tolerate jitter up to certain specified limits. Figure 23 shows the tolerance curve and the actual measured data for the device. FIGURE 23. INPUT JITTER TOLERANCE FOR E3
64 JITTER AMPLITUDE (UI pp) 10 1.5
ITU-T G.823 XRT75L00
0.3
0.1
1 JITTER FREQUENCY (kHz)
10
800
The Figure 11 below shows the jitter amplitude versus the modulation frequency for various standards.
34
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
BIT RATE (KB/S) 34368 44736 44736 51840 INPUT JITTER AMPLITUDE (UI P-P) STANDARD A1 ITU-T G.823 GR-499 CORE Cat I GR-499 CORE Cat II GR-253 CORE Cat II 1.5 5 10 15 A2 0.15 0.1 0.3 1.5 A3 0.15
F1(HZ) F2(HZ) F3(KHZ) F4(KHZ) F5(KHZ)
MODULATION FREQUENCY
100 10 10 10
1000 2.3k 669 30
10 60 22.3 300
800 300 300 2
20
6.2
JITTER TRANSFER - RECEIVER/TRANSMITTER:
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency. There are two distinct characteristics in jitter transfer: jitter gain (jitter peaking) defined as the highest ratio above 0 dB; and jitter transfer bandwidth.The overall jitter transfer bandwidth is controller by a low bandwidth loop,which is part of the XRT75L00.. The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer indicates the element added jitter.A zero dB jitter transfer indicates the element had no effect on jitter. Table 12 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates. TABLE 12: JITTER TRANSFER SPECIFICATIONS
E3 ETSI TBR-24 DS3 GR-499 CORE section 7.3.2 Category I and Category II STS-1 GR-253 CORE section 5.6.2.1
The XRT75L00 meets the above Jitter Specifications. 6.3 JITTER GENERATION: Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set according to the data rate. In general, the jitter is measured over a band of frequencies. 6.4 Jitter Attenuator: An advanced crystal-less jitter attenuator is included in the XRT75L00. The jitter attenuator uses the internal reference clock. In Host mode, by clearing or setting the JATx/Rx bit in the control register selects the jitter attenuator either in the Receive or Transmit path. In Hardware mode, JATx/Rx pin selects the jitter attenuator in Receive or Transmit path. The FIFO is either a 16-bit or 32-bit register. In Host mode, the bits JA0 and JA1can be set to appropriate combination to select the different FIFO sizes or to disable the jitter attenuator. In Hardware mode, appropriate setting of the pins JA0 and JA1 selects the different FIFO sizes or disable the jitter attenuator. Data is clocked into the FIFO with the associated clock signal (TxClk or RxClk) and clocked out of the FIFO with the dejittered
35
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL is set to "1" in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts of jitter.
Table 13 specifies the jitter transfer mask requirements for various data rates.
TABLE 13: JITTER TRANSFER PASS MASKS
RATE (KBITS) 34368 44736 MASK G.823 ETSI-TBR-24 GR-499, Cat I GR-499, Cat II GR-253 CORE GR-253 CORE F1 (HZ) 100 F2 (HZ) 300 F3 (HZ) 3K F4 (KHZ) 800K A1(dB) 0.5 A2(dB) -19.5
10 10 10 10
10k 56.6k 40 40k
-
15k 300k 15k 400k
0.1 0.1 0.1 0.1
-
51840
The jitter attenuator within the XRT75L00 meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the Figure 24. FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
JITTER AMPLITUDE
A1 A2
F1
F2
F3
F4
J IT T E R F R E Q U E N C Y (k H z )
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
7.0 SERIAL HOST INTERFACE: A flexible serial microprocessor interface is incorporated in the XRT75L00. The interface is generic and is designed to support the common microprocessors/microcontrollers. The XRT75L00 operates in Host mode when the HOST/HW pin is tied "High". The serial interface includes a serial clock (SClk), serial data input (SDI), serial data output (SDO), chip select (CS) and interrupt output (INT). The serial interface timing is shown in Figure 11. The active low interrupt output signal (INT pin) indicates alarm conditions like LOS, DMO and FL to the processor. When the XRT75L00 is configured in Host mode, the following input pins,TxLEV, TAOS, RLB, LLB, E3, STS-1/ DS3, REQEN, JATx/Rx, JA0 and JA1 are disabled and must be connected to ground. Table 14 below illustrates the functions of the shared pins in either Host mode or in Hardware mode. TABLE 14: FUNCTIONS OF SHARED PINS
PIN NUMBER 24 26 25 27 28 IN HOST MODE CS SClk SDI SDO INT IN HARDWARE MODE RxClkINV TxClkINV RxON RxMON LOSMUT
NOTE: While configured in Host mode, the TxON input pin will be active if the TxON bit in the control register is set to "1", and can be used to turn on and off the transmit output drivers. This permits a system designed for redundancy to quickly switch out a defective line card and switch-in the backup line card.
TABLE 15: REGISTER MAP AND BIT NAMES
ADDRESS (HEX) 0x00 PARAMETER NAME DATA BITS 7 6 5 Reserved 4 RxON 3 2 1 0 TxON
APS/Redundancy Reserved Reserved (read/write) Interrupt Enable (read/write) Interrupt Status (reset on read) Alarm Status (read only) Transmit Control (read/write) Receive Control (read/write) Block Control (read/write) Jitter Attenuator (read/write) Reserved
Reserved Reserved Reserved
0x01
CNT_SATIE PRBSIE
FLIE
RLOLIE
RLOSIE
DMOIE
0x02
Reserved
CNT_SATIS PRBSIS
FLIS
RLOLIS
RLOSIS
DMOIS
0x03
Reserved PRBSLS
DLOS
ALOS
FL
RLOL
RLOS
DMO
0x04
Reserved
TxMON
INSPRBS Reserved
TAOS
TxClkINV
TxLEV
0x05
Reserved
DLOSDIS
ALOSDIS RxClkINV LOSMUT
RxMON
REQEN
0x06
Reserved
PRBSEN
RLB
LLB
E3
STS1/ DS3 JATx/Rx
SR/DR
0x07
Reserved
PNTRST
JA1
JA0
37
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR TABLE 15: REGISTER MAP AND BIT NAMES
ADDRESS (HEX) 0x080x1F 0x20 Interrupt EnableGlobal (read/write) Interrupt Status (read only) Reserved PRBS Error Count (MSB) PRBS Error Count (LSB) MSB MSB Reserved PRBS Holding MSB Reserved Chip_id (read only) Chip_version (read only) Device part number (7:0) PARAMETER NAME DATA BITS 7 6 5 4 Reserved Reserved Reserved Reserved 3 2 1
REV. 1.0.2
0
INTEN
0x21
Reserved
Reserved Reserved
INTST
0x220x2F 0x30 0x31 0x32-0x37 0x38 0x390x3D 0x3E
Reserved LSB LSB
LSB
0x3F
Chip revision number (7:0)
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REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS (HEX) 0x00 TYPE R/W BIT LOCATION D0 SYMBOL RxON DESCRIPTION Bit 4 = RxON, Receiver Turn On. Writing a "1" to the bit field turns on the Receiver and a "0" turn off the Receiver. Bit 0 = TxON, Transmitter Turn On. Writing a "1" to the bit field turn on the Transmitter. Writing a "0" turns off the transmitter and tri-state the transmitter output (TTIP/TRing). Writing a "1" to this bit field enables the DMO interrupt and triggers an interrupt when the transmitter driver fails. Writing a "0" disables the interrupt. Writing a "1" to this bit field enables the RLOS interrupt and triggers an interrupt when the RLOS condition occurs. Writing a "0" disables the interrupt. Writing a "1" to this bit field enables the RLOL interrupt and triggers an interrupt when RLOL condition occurs. Writing a "0" disables the interrupt. Writing a "1" to this bit field enables the FL interrupt and triggers an interrupt when the FIFO Limit of the Jitter Attenuator is within 2 bits of overflow/underflow condition. Writing a "0" disables the interrupt. DEFAULT VALUE(BIN) 0
D4
TxON
0
0x01
R/W
D0
DMOIE
0
D1
RLOSIE
0
D2
RLOLIE
0
D3
FLIE
0
NOTE:
D4 D5 PRBSIE CNT_SATIE
This bit field is ignored when the Jitter Attenuator is disabled.
0 0
Writing a "1" to this bit enables the PRBS bit error interrupt. Writing a "1" to this bit enables the PRBS errorcounter saturation interrupt. When the PRBS error counter reaches 0xFFFF, an interrupt will be generated.
39
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS (HEX) 0x02 TYPE Reset Upon Read BIT LOCATION D0 SYMBOL DMOIS DESCRIPTION This bit is set to "1" every time a DMO status change has occurred since the last cleared interrupt.This bit is cleared when read. This bit is set to "1" every time a RLOS status change has occurred since the last cleared interrupt. This bit is cleared when read. This bit is set to "1" every time a RLOL status change has occurred since the last cleared interrupt. This bit is cleared when read. This bit is set to "1" every time a FIFO Limit status change has occurred since the last cleared interrupt. This bit is cleared when read. This bit is set to "1" when a PRBS bit error detected. This bit is cleared when read. is
REV. 1.0.2
DEFAULT VALUE(BIN) 0
D1
RLOSIS
0
D2
RLOLIS
0
D3
FLIS
0
D4 D5 0x03 Read Only D0
PRBSIS CNT_SATIS DMO
0 0 0
This bit is set to "1" when the PRBS error counter has saturated (0xFFFF). This bit is cleared when read. This bit is set to "1" every time the MTIP/MRing input pins have not detected any bipolar pulses for 128 consecutive bit periods. This bit is set to "1" every time the receiver declares an LOS condition. This bit is set to "1" every time when the receiver declares a Loss of Lock condition. This bit is set to "1" every time the FIFO in the Jitter Attenuator is within 2 bit of underflow/overflow condition. This bit is set to "1" every time the receiver declares Analog LOS condition. This bit is set to "1" every time the receiver declares Digital LOS condition. This bit is set to "1" every time the PRBS detects a bit error.
D1 D2 D3
RLOS RLOL FL
0 0 0
D4 D5 D6
ALOS DLOS PRBSLS
0 0 0
40
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS (HEX) 0x04
TYPE R/W
BIT LOCATION D0
SYMBOL TxLEV
DESCRIPTION Writing a "1" to this bit disables the Transmit Build-out circuit and writing a "0" enables the Transmit Build-out circuit.
DEFAULT VALUE(BIN) 0
NOTE: See section 4.03 for detailed description.
D1 TxClkINV Writing a "1" to this bit configures the transmitter to sample the data on TPData/TNData input pins on the rising edge of TxClk. Setting this bit to "1" causes a continuous stream of marks to be sent out at the TTIP and TRing pins. This Bit Location is Not Used. Writing a "1" to this bit causes the PRBS generator to insert a single-bit error onto the transmit PRBS data stream. 0 0
D2 D3 D4
TAOS Reserved INSPRBS
0
NOTE: PRBS Generator/Detector must be enabled for this bit to have any effect.
D5 TxMON When this bit is set to "1", the driver monitor is connected to its own transmit channel and monitors the transmit driver. When a transmit failure is detected, the DMO output will go high. When this bit is "0", MTIP and MRing can be connected to other transmit channel for monitoring. Setting this bit to "1" enables the Receive Equalizer . 0
0x05
R/W
D0
REQEN
0
NOTE: See section 2.01 for detailed description.
D1 RxMON Writing a "1" to this bit configures the Receiver into monitoring mode. In this mode, the Receiver can monitor a signal at the RTIP/RRing pins that be attenuated up to 20dB flat loss. Writing a "1" to this bit causes the RPOS/RNEG outputs to be grounded while the LOS condition is declared. 0
D2
LOSMUT
0
NOTE: If this bit has ben set, it will remain set evan after LOS condition is cleared.
D3 D4 D5 RxClkINV ALOSDIS DLOSDIS Writing a "1" to this bit configures the Receiver to output RPOS/RNEG data on the falling edge of RxClk. Writing a "1" to this bit disables the ALOS detector. Writing a "1" to this bit disables the DLOS detector. 0 0 0
41
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS (HEX) 0x06 TYPE R/W BIT LOCATION D0 D1 SYMBOL SR/DR STS-1/DS3 DESCRIPTION Writing a "1" to this bit configures the Receiver and Transmitter into Single-Rail (NRZ) mode. Writing a "1" to this bit configures the channel 0 into STS-1 mode.
REV. 1.0.2
DEFAULT VALUE(BIN) 0 0
NOTE: This bit field is ignored if the chip is configured to operate in E3 mode.
D2 D3 D4 E3 LLB RLB Writing a "1" to this bit configures the chip in E3 mode. Writing a "1" to this bit configures the chip in Local Loopback mode. Writing a "1" to this bit configures the chip in Remote Loopback mode. 0 0 0
RLB 0 0 1 1
LLB 0 1 0 1
Loopback Mode Normal Operation Analog Local Remote Digital
D5
PRBSEN
Writing a "1" to this bit enables the PRBS generator/ detector.PRBS generator generate and detect either 215-1 (DS3 or STS-1) or 223-1 (for E3). The pattern generated and detected are unframed pattern. This bit along with JA1 bit configures the Jitter Attenuator as shown in the table below.
0
0x07
R/W
D0
JA0
0
JA0 0 0 1 1
JA1 0 1 0 1
Mode 16 bit FIFO 32 bit FIFO Disable Jitter Attenuator Disable Jitter Attenuator
D1 D2 D3
JATx/Rx JA1 PNTRST
Writing a "1" to this bit selects the Jitter Attenuator in the Transmit Path. A "0" selects in the Receive Path. This bit along with the JA0 configures the Jitter Attenuator as shown in the table. Setting this bit to "1" resets the Read and Write pointers of the jitter attenuator FIFO.
0 0 0
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XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS (HEX) 0x08
TYPE
BIT LOCATION
SYMBOL Reserved
DESCRIPTION
DEFAULT VALUE(BIN)
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL
ADDRESS (HEX) 0x20 0x21 TYPE R/W Read Only BIT LOCATION D0 D0 SYMBOL INTEN INTST DESCRIPTION Bit 0 = INTEN Writing a "1" to this bit enables the interrupts. Bit 0 = INTST bit is set to "1" if an interrupt service is required. The source level interrupt status register is read to determine the cause of interrupt. Reserved Reset Upon Read Reset Upon Read D[7:0] PRBSmsb PRBS error counter MSB [15:8] DEFAULT VALUE(BIN) 0 0
0x22 0x2F 0x30
0x31
D[7:0]
PRBSlsb
PRBS error counter LSB [7:0]
0x320x37 0x38 0x390x3D 0x3E 0x3F Read Only Read Only D[7:0] D[7:0] Chip_id Read Only D[7:0] PRBShold
Reserved PRBS Holding Register Reserved This read only register contains device id. 01110001 00000001
Chip_version This read only register contains chip version number
43
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 8.0 DIAGNOSTIC FEATURES: 8.1 PRBS Generator and Detector:
REV. 1.0.2
The XRT75L00 contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for diagnostic purpose. This feature is only available in Host mode. With the PRBSEN bit = "1", the transmitter will send out PRBS of 223-1 in E3 rate or 215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS detector is also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go "Low" to indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the PRBSLS bit will be set to "1" and RNEG/LCV pin will go "High". With the PRBS mode enabled, the user can also insert a single bit error by toggling "INSPRBS" bit. This is done by writing a "1" to INSPRBS bit. The receiver at RNEG/LCV pin will pulse "High" for half RxClk cycle for every bit error detected. Any subsequent single bit error insertion must be done by first writing a "0" to INSPRBS bit and followed by a "1". When PRBS mode is enabled, the PRBS counter starts counting each single bit error. The PRBS counter is 16 bits wide. The current value in the counter can be read via two readback operations of the Serial I/O registers. 1) Either the Least Significant Byte (LSB, address 0x30) or the Most Significant Byte (MSB, address 0x31) can be read first. The value of the un-read register will be copied into the Holding register (address 0x38) and both the LSB and MSB registers will be reset to zero. 2) Read the Holding register and concatenate the result with the value from the first read operation to get the full 16 bit counter value. When the PRBS mode is first enabled, errors will be counted while the receiver logic is synchronizing to the PRBS pattern. When RNEG/LCV goes "Low" indicating PRBS synchronization, reset the counter by reading either the LSB or the MSB register. Figure 25 shows the status of RNEG/LCV pin when the XRT75L00 is configured in PRBS mode. FIGURE 25. PRBS MODE
RClk
SYNC LOSS
RNEG/LCV
PRBS SYNC Single Bit Error
8.2
LOOPBACKS:
The XRT75L00 offers three loopback modes for diagnostic purposes. In Hardware mode, the loopback modes are selected via the RLB and LLB pins. In Host mode, the RLB and LLB bits in the control registers select the loopback modes. 8.2.1 ANALOG LOOPBACK: In this mode, the transmitter outputs (TTIP and TRING) are connected internally to the receiver inputs (RTIP and RRING) as shown in Figure 26. Data and clock are output at RCLK, RPOS and RNEG pins for the corresponding transceiver. Analog loopback exercises most of the functional blocks of the device including the jitter attenuator which can be selected in either the transmit or receive path. XRT75L00 can be configured in Analog Loopback either in Hardware mode via the LLB and RLB pins or in Host mode via LLB and RLB bits in the channel control registers.
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REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
NOTES: 1. In the Analog loopback mode, data is also output via TTIP and TRING pins. 2. Signals on the RTIP and RRING pins are ignored during analog loopback.
FIGURE 26. ANALOG LOOPBACK
TCLK TPDATA TNDATA HDB3/B3ZS1 ENCODER
JITTER 2 ATTENUATOR
TIMING CONTROL
TTIP Tx TRING
RCLK RPOS RNEG
1 2
JITTER 2 ATTENUATOR
HDB3/B3ZS1 DECODER
DATA & CLOCK RECOVERY
RTIP Rx RRING
if enabled if enabled and selected in either Receive or Transmit path
8.2.2
DIGITAL LOOPBACK:
The Digital Loopback function is available either in Hardware mode or Host mode. When the Digital Loopback is selected, the transmit clock (TxClk) and transmit data inputs (TPDATA & TNDATA) are looped back and output onto the RxClk, RPOS and RNEG pins as shown in Figure 27. The data presented on TxClk, TPDATA and TNDATA are not output on the TTIP and TRING pins.This provides the capability to configure the protection card (in redundancy applications) in Digital Loopback mode without affecting the traffic on the primary card.
NOTE: Signals on the RTIP and RRING pins are ignored during digital loopback.
FIGURE 27. DIGITAL LOOPBACK
TCLK TPDATA TNDATA
1 HDB3/B3ZS ENCODER
JITTER 2 ATTENUATOR
TIMING CONTROL
TTIP Tx TRING
RCLK RPOS RNEG
1 2
JITTER 2 ATTENUATOR
1 HDB3/B3ZS DECODER
DATA & CLOCK RECOVERY
RTIP Rx RRING
if enabled if enabled and selected in either Receive or Transmit path
45
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR 8.2.3 REMOTE LOOPBACK:
REV. 1.0.2
With Remote loopback activated as shown in Figure 28,the receive data on RTIP and RRING is looped back after the jitter attenuator (if selected in receive or transmit path) to the transmit path using RxClk as transmit timing. The receive data is also output via the RPOS and RNEG pins. During the remote loopback mode, if the jitter attenuator is selected in the transmit path, the receive data after the Clock and Data Recovery Block is looped back to the transmit path and pass through the jitter attenuator using RxClk as the transmit timing.
NOTE: Input signals on TxClk, TPDATA and TNDATA are ignored during Remote loopback.
FIGURE 28. REMOTE LOOPBACK
TCLK TPDATA TNDATA HDB3/B3ZS ENCODER
1
JITTER 2 ATTENUATOR
TIMING CONTROL
TTIP Tx TRING
RCLK RPOS RNEG
1 2
JITTER 2 ATTENUATOR
HDB3/B3ZS DECODER
1
DATA & CLOCK RECOVERY
RTIP Rx RRING
if enabled if enabled and selected in either Receive or Transmit path
8.3
TRANSMIT ALL ONES (TAOS):
Transmit All Ones (TAOS) can be set either in Hardware mode by pulling the TAOS pins "High" or in Host mode by setting the TAOS control bits to "1" in the Channel control registers. When the TAOS is set, the Transmit Section generates and transmits a continuous AMI all "1's" pattern on TTIP and TRING pins. The frequency of this "1's" pattern is determined by TClk.TAOS data path is shown in Figure 29. FIGURE 29. TRANSMIT ALL ONES (TAOS)
TCLK TPDATA TNDATA
1
JITTER 2 ATTENUATOR
HDB3/B3ZS ENCODER
TIMING CONTROL
Tx
TTIP Transmit All 1 TRING
TAOS
RCLK RPOS RNEG
1 2
JITTER 2 ATTENUATOR
1
HDB3/B3ZS DECODER
DATA & CLOCK RECOVERY
RTIP Rx RRING
if enabled if enabled and selected in either Receive or Transmit path
46
REV. 1.0.2
XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
ORDERING INFORMATION
PACKAGE DIMENSIONS
PART NO. XRT75L00IV PACKAGE 52 Pin TQFP (10mm x 10mm) OPERATING TEMPERATURE RANGE -40C to +85C
D D1 39 27
40
26
D1
D
52
14
1 B e A2
13
C A Seating Plane A1 L
Note: The control dimension is the millimeter column
INCHES SYMBOL A A1 A2 B C D D1 e L aaa MIN 0.055 0.002 0.053 0.009 0.004 0.465 0.390 0.018 0 7 typ 0.003 MAX 0.063 0.006 0.057 0.015 0.008 0.480 0.398 0.030 7 MILLIMETERS MIN 1.40 0.05 1.35 0.22 0.09 11.80 9.90 0.45 0 7 typ 0.08 MAX 1.60 0.15 1.45 0.38 0.20 12.20 10.10 0.75 7
0.0256 BSC
0.65 BSC
47
XRT75L00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.2
REVISION HISTORY
1.0.1 Removed evaluation schematic. 1.0.2 Changed the Device ID to reflect the correct value.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2004 EXAR Corporation Datasheet February 2004. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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